Design Of Modulo − Multipliers Using DR-RNS Based On Radix-8 Booth Encoded Algorithm

Modular arithmetic operations l ike inversion, multiplication and exponentiation are used in several cryptography applications. A special modulo set of forms {21,2,2+1}are preferred over the generic modulo due to the ease of hardware implementation of modulo arithmetic functions as well as systemlevel intermodulo operations, such as RNS-to-binary conversion and sign detections. Key sizes in the range of 512~1024 bits and 160~512 bits are typical in RSA and ECC, respectively. With this precept, a family of radix 8 Booth encoded modulo 21 multipliers, with delay adaptable to the RNS multiplier delay, is proposed.The adaptive delay of the proposed family of multipliers is corroborated by CMOS implementations.RNS multiplier, when the critical modulo multiplier delay is significantly greater than the noncritical modulo 2 − 1 multiplier delay.Thefirst-everfamilyoflowareaandlow-powerradix-8Boothen codedmodulo21 multiplier whose delay can be tuned to match the RNS delay closely has been proposed in this paper. ACSA tree with end-around-carry addition for accumulation of redundant partial products and a Sklan sky parallel-prefix structure has also been implemented. Key word: Booth algorithm, design space exploration, modulo arithmetic, multiplier, residue number system (RNS).